VERILOG FSM Sequence Generator Next State Function

The next_pattern module provides the next state function for a sequence generator. The module outputs the next state given as the input the current state. In this example, an input of 0 would produce 1, an input of 1 would produce 3, and so on. Implement the next_pattern with either gates or Boolean expressions.

The next_pattern module provides the next state function for a Finite State Machine (FSM) that generates the following sequence of patterns:

0, 1, 3, 2

The first pattern follows the last pattern.

Any patterns not in the sequence should be considered as do not cares. The next function will not be tested for these patterns.

Verilog Code to implement:

module next_pattern(output logic [1:0] next, input logic [1:0] cur);

endmodule