Verilog State Machine Project.

FPGA Board : INTEL DE10-Lite.

Program: Quartus Prime

I/O pins:

input ADC_CLK_10,

input MAX10_CLK1_50,

input MAX10_CLK2_50,

//////////// SEG7 //////////

output [7:0] HEX0,

output [7:0] HEX1,

output [7:0] HEX2,

output [7:0] HEX3,

output [7:0] HEX4,

output [7:0] HEX5,

input [1:0] KEY,

output [9:0] LEDR,

input [9:0] SW

II. Project Overview

Details not specified in this lab should be chosen by you. The input signals for the design are:

KEY0 reset resets all state so that it is ready to begin a race

KEY1 a) start begins countdown

b) finish for each athlete

HEX5 Shows medal type of first three finishers: G first place, S second place, B third place, fourth place and later. It is always blank except when showing the medal type won by a finisher.

HEX4HEX0 Counter that counts time up from zero to a maximum of 14.999 seconds. It consists of two integer digits and three fractional digits; all base10.The circuit operates as follows:

When the reset key is pressed, the circuit is prepared to begin the race

When the start key is pressed, HEX3 counts down from 3 - 2 - 1 - 0. All other HEX displays are blank.

When the counter reaches zero, HEX4HEX0 function as a XX.XXX base10 stopwatch counting up by thousandths of a second as accurately as possible.

If the finish button is pressed (KEY1), several things happen:

For exactly one second, the HEX4HEX0 display shows the exact time the finish button was pressed

HEX5 shows the medal type as described earlier

The counter continues to count time without being shown on the display

After exactly one second, the display continues counting as if the finish button was never pressed

For example: if the finish button is first pressed at 8.537 seconds, the display would show G 8537 (notice blank segment for times less than 10 seconds) for exactly one second and then continue counting at 9.537

For example: if the finish button is first pressed at 11.126 seconds, the display would show G11126 for exactly one second and then continue counting at 12.126

If the finish button is pressed (KEY1) more than once:

The function is the same as when pressed the first time except:

The medal type is calculated appropriately

If less than one second has passed since the first press of finish, the previous time is not shown a full second; instead the time of the last press of finish is immediately shown, lasting for one second.

When the timer reaches 14.999 seconds, it holds that value and all ten LEDs LEDR9LEDR0 are flashed together at 4 Hertz until reset is asserted. Your circuit must be able to handle the timing for at least four athletes.

CLOCKING

Precisely control the timing of your circuit using the same method used in the previous lab. Although the boards 50 MHz clock can be slowed using a PLL, it can not be slowed enough to clock the timer directly. Therefore, use a counter to enable your logic. For example, the output of a 50 MHz ring counter that counts to one million would have a unique value once every 0.02 seconds or 50 Hertz. Your entire circuit should be clocked by the default 50 MHz clock and you may not modify this clock signal.