Design and develop a Verilog state machine to control the Traffic Lights system of a busy highway. Consider

a

$4$

$-$

road junction with the traffic control system installed on a highway junction with left and right turns

leading to side

$-$

ways

$($

service roads

$)$

$-$

$$Left turn is always free while right turn needs a signal.

For simplicity, assume that all are one

$-$

ways for traffic movement

$-$

$$as indicated in the diagram below.

Ensure that the FSM controller supports the below listed functionality and features by calling out any

assumptions made in the process:

$-$

$1$

$.$

$$Regular operation of the traffic lights with a delay of

$6$

$0$

$$seconds for each state switch

$/$

transition in a

round

$-$

robin fashion.

$2$

$.$

$$Interrupt #

$1$

$-$

$$support movement of life services like Ambulance, Fire Service trucks

$-$

$$The controller

should automatically allow the traffic to flow as soon as they are detected on the highway, as the

interrupt with highest priority.

$3$

$.$

$$Interrupt #

$2$

$-$

$$divert the onward traffic from highway to the

$2$

$$side lanes, there by clearing the main

highway to facilitate emergency VIP movement.

$4$

$.$

$$Ensure that the controller has priority among the interrupt scenarios, in case of collision.

$5$

$.$

$$Ensure that the controller state machine recovers

$/$

reboots after detecting any of the

$2$

$$interrupt

scenarios stated above

$$

as a fail

$-$

safe controller machine. PROVIDE TESTBENCH FOR THIS WITH EXPLANATION

testbench must have clk change also but expert had provided without clock change testbench. just clock connection is provid