Vesp 1.0 is an example CPU that is designed to help explain the operation of a Von Neumann processor. It is a hybrid; some instructions have a zero-address format, some have one-address format, and one has a two-address format. Its instruction repertoire has 8 instructions. It uses a 16-bit instruction format. The left most three bits specify the op-code. The remaining bits are either left unused or they specify an address. Two of the instructions (LDA and MOV) are defined by two 16-bit words. Its memory consists of 65536 locations (16-bit address space) It has a 16-bit program counter (PC) and 16-bit instruction register (IR) Instruction Set Architecture of A Very Simple Processor (VESP 1.0) Write a self-modifying program in Vesp 1.0 to subtract an array of numbers stored in memory locations 0 times 100 through 0 times 11 F from an array of numbers stored in memory locations 0 times 200 through 0 times 21 F. The results must be stored in locations 0 times 100 through 0 times 11 F. Vesp 1.0 is an example CPU that is designed to help explain the operation of a Von Neumann processor. It is a hybrid; some instructions have a zero-address format, some have one-address format, and one has a two-address format. Its instruction repertoire has 8 instructions. It uses a 16-bit instruction format. The left most three bits specify the op-code. The remaining bits are either left unused or they specify an address. Two of the instructions (LDA and MOV) are defined by two 16-bit words. Its memory consists of 65536 locations (16-bit address space) It has a 16-bit program counter (PC) and 16-bit instruction register (IR) Instruction Set Architecture of A Very Simple Processor (VESP 1.0) Write a self-modifying program in Vesp 1.0 to subtract an array of numbers stored in memory locations 0 times 100 through 0 times 11 F from an array of numbers stored in memory locations 0 times 200 through 0 times 21 F. The results must be stored in locations 0 times 100 through 0 times 11 F