Question: vhdl code for: Using two processes (without sensitivity lists) in your test bench, recreate my test bench. The first process is a clock process where

vhdl code for: Using two processes (without sensitivity lists) in your test bench, recreate my test bench. The first process is a clock process where the clock is enabled by a Boolean signal simulationActive. The second process will generate the inputs to the counter and check the counter outputs to confirm the counters operates as expected.

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