VHDL gate level homework need vhdl code for an 8 bit divider that takes in 2 8bit signals A and B and produces an 8 bit output RESULT that is equals to (A / B).

this divider must be asynchronous designed and implemented on gate level.

DO NOT IMPLEMENT THE BEHAVIORAL 8BIT DIVIDER.

NOTE: THE DIVIDER MUST BE ASYNCHRONOUS --> MEANING NO CLOCKS

AND IT IS NOT ALLOWED TO USE ANY HIGH LEVEL OPERANDS LIKE +,-,*,/ OR SUCH

please explain how it works aswell *** <=== its very important that you explain the code ****

please type down the code so its readable,

thanks alot