Question: VHDL : Write a short testbench for the code listed below that deals with keyboard scan codes. Only choose 1 key for example. entity top

VHDL : Write a short testbench for the code listed below that deals with keyboard scan codes. Only choose 1 key for example.

entity top is PORT (USB_CLK: in STD_ULOGIC; USB_DATA: in STD_ULOGIC); end top;

architecture Behavioral of top is

signal bitCount : integer range 0 to 100 := 0; signal scancodeReady : STD_LOGIC := '0'; signal scancode : STD_LOGIC_VECTOR (7 downto 0); signal breakReceived : STD_LOGIC := '0'; begin keyboard_scan_ready_enable : process(USB_CLK) is begin if falling_edge(USB_CLK) then if bitCount = 0 AND USB_DATA = '0' then scancodeReady <= '0'; bitCount <= bitCount + 1; elsif bitCount >0 and bitCount <9 then scancode <= USB_DATA & scancode (7 downto 1); bitCount <= bitCount + 1; elsif bitCount = 9 then bitCount <= bitCount +1; elsif bitCount = 10 then scancodeReady <= '1'; bitCount <= 0; end if; end if; end process keyboard_scan_ready_enable; scan_keyboard : process (scancodeReady, scancode) is begin if rising_edge(scancodeReady) then if breakReceived ='1' then breakReceived <= '0'; elsif breakReceived ='0' then if scancode = "11110000" then breakReceived <= '1'; end if; end if;

scancode <= scancode (3 downto 0); end if; end process scan_keyboard; end behavioral;

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