Vivado is the software required to perform the simulation on

Task 1: One-bit Full Comparator: 1. Complete the truth table for one-bit full comparator with equal, greater than and less than outputs. Table 1 One-bit full comparator AD (-) w y) 0 0 1 0 1 0 1 1 1 1 0 0 1. Derive the Boolean functions describing this one bit full comparator outputs (you can use Kamoph map) 2. Using the skeletal code provided below, add the body of the one-bit comparator. 1/ comp. // Sample interface for 1-bit full comparator // 1-bit full comparator // module compla, b, y.w.2k input a b; outputzw.y: 1/ Body / define behavior of one-bit comparator endmodule 2. Simulate and implement the Verilog design for one-bit comparator. 3. Use switches and LEDs to test and demonstrate your circuit to the lab instructor. 4. Copy your codes, simulation and testing cases to your report