We consider a n$-$channel MOSFET with n$+$ polysilicon gate $($which implies that EF $=$ Ec$).$ The acceptor concentration in the semiconductor is $4\mathrm{.}21018$ cm$-3.$ The oxide thickness is $10$ nm$.$ For the moment we assume that there is no trapped charge in the oxide. $($a$)(4$pts$)$ Calculate the threshold voltage of this device and draw the band diagram at threshold voltage. $($b$)(4$pts$)$ Replace the oxide with silicon nitride, Si$3$N$4($Si$3$N$4=7\mathrm{.}5)$ and maintain the thickness of gate dielectric layer. Calculate new EOT of this MOSFET. $($c$)(4$pts$)$ A disadvantage of Si$3$N$4$ is the trapped positive charge at the interface between the insulator and in case this trapped charge has a density of $1\mathrm{.}01012/$cm$2,$ which Si$3$N$4$ thickness is required to maintain the threshold voltage as in question $($a$).($d$)(4$pts$)$ If S$/$D distance is $1$um$,$ what is the punch$-$through voltage of $($a$)($e$)(4$pts$)$ Is VDS$=2$V$,$ the device under SCLT$?$