We create a software model to study how our program would on a multi-core chip where each of the cores runs at 2 GHz like the original. We discover that as we can spread the arithmetic and load/store instructions out over multiple cores but there is a bit of a tax for coordinating things, and so we will run 0.7x p (where p is the number of processors) on each core for each of these two instruction classes. The number of branch instructions per processor remains unchanged. So, for example, if we run on 2 cores, each will run n/(0.7x2) arithmetic instructions, where n is the number of original arithmetic instructions. (20x0.5-10 pts) [5] Find the total execution time for this program on 1, 2, 4, and 8 cores, and show the relative speedup of the 2, 4, and 8 core result relative to the single processor result. Use the following table for your answers, and also include the equation you use to calculate execution time in terms of all of the instruction types and CPI values. a. exec #arith CPI #L/S CPI #branch CPI cycles time speedup instr Arith instr L/S instr Branch 1 2.56E+09 1.28E+09 12 2.56E+08 12 12 12 4 b. (20x0.5-10 pts) [10] COD S81.6, 1.8> If the CPI of the arithmetic instructions was doubled, what would the impact be on the execution time of the program on 1, 2,4, or 8 processors? You may use the full table or simply list the new execution times exec #arith CPI #L/S CPI #branch CPI P instr Arith instr /S instr Branch cy cycles time speedup 1 2.56E+09 2 1.28E+09 12 2.56E+08 c. (5 pts) [10] What value of load/store CPI would allow a single processor to match the performance of four processors from part (a)