Question: We have a 8-lines of L1 data cache. Let us assume each line has 256 bits and memory addresses have 16 bits of width, with

We have a 8-lines of L1 data cache. Let us assume each line has 256 bits and memory addresses have 16 bits of width, with byte-addressable memory. Indexing the cache is implemented by lowest-order bits.

-Let us assume that the level 1 data cache has a hit rate of 30% on your application, an access time of a single cycle, and a miss penalty to memory will be of 30 cycles.

What will the AMAT time?

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