Question: We have a 8-lines of L1 data cache. Let us assume each line has 256 bits and memory addresses have 16 bits of width, with

We have a 8-lines of L1 data cache. Let us assume each line has 256 bits and memory addresses have 16 bits of width, with byte-addressable memory. Indexing the cache is implemented by lowest-order bits.

-We want to increase the performance and we add a L2 cache to the system, what should the access time of the L2 cache with a hit rate of 50% in order to reduce the AMAT?

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