Question: we have a block that takes a clock as an input, it generates two clocks in the output, first clock has a frequency of 1

we have a block that takes a clock as an input, it generates two clocks in the output, first clock has a frequency of 1/2th (half) of the input clock and 2nd has frequency of 1/4th of the input clock write a verilog code that implements this diagram.

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