We pointed out that l/O buses do not need separate address lines. Construct a timing diagram similar to Fiqure 7.7 that describes the handshake between arn /O controller and a disk controller for a write operation. (Hint: You will need to add a control signal.) Request II Address Write/Read Ready Data Clock Figure 7.7: A Bus Timing Diagram We pointed out that l/O buses do not need separate address lines. Construct a timing diagram similar to Fiqure 7.7 that describes the handshake between arn /O controller and a disk controller for a write operation. (Hint: You will need to add a control signal.) Request II Address Write/Read Ready Data Clock Figure 7.7: A Bus Timing Diagram