***We use the Quartus software, I am unsure how to convert from the truth table to a code on that software. Thank you for the help!!****

Consider the given design schematic. Create a truth table and find the output y for all possible combinations of the input signals. Using K-map, find the switching function of the design. Using Verilog gate level primitives, develop a structural model using Verilog code that describes the logic circuit given in the schematics. Your Verilog code should be well documented using comments. Use the RTL Viewer to verify the structural design created using the Verilog code. Did the synthesis tool follow the hardware design description, or did it implement any modifications? For the same functionality, can the design be optimized? A B CE Y DE