We want to design a sequence detector for detecting "001". The sequence detector checks the values of the one-bit input, X, at every positive edge of the CLK signals and as soon as the 3-bit sequence "001" is found on X, the output, Z, goes high for one clock cycle.

A partial Verilog code of the design is given below:

module exam(clk, X, Z);

input clk, X;

output Z;

reg Z;

reg [1:0] state, NextState;

initial begin

state = 0;

NextState = 0;

end

alwasy@(poseegde clk)

state

always@(*)

begin

//missing part

end

endmodule

Which answer is a correct code for the missing body of the always@(*) block?

Select one:

a. case(state) 0: If(!X) NextState=1 else NextState=0; 1: If(X) NextState=0 else NextState=2; 2: If(X) begin NextState=0; Z=1; end else NextState=2; endcase

b. None of these are correct.

c. Z = 0; case(state) 0: If(~X) NextState=1; 1: If(~X) NextState=2; 2: If(X) begin NextState=0; Z=1; end endcase

d. Z = 0; case(state) 0: If(!X) NextState=1; 1: If(X) NextState=0 else NextState=2; 2: If(X) begin NextState=0; Z=1; end endcase

e. case(state) 0: If(!X) NextState=1; 1: If(X) NextState=0 else NextState=2; 2: If(X) begin NextState=0; Z=1; end endcase

Which answer is a correct code for the missing body of the always@(*) block?

Select one:

a. case(state) 0: If(!X) NextState=1 else NextState=0; 1: If(X) NextState=0 else NextState=2; 2: If(X) begin NextState=0; Z=1; end else NextState=2; endcase

b. None of these are correct.

c. Z = 0; case(state) 0: If(~X) NextState=1; 1: If(~X) NextState=2; 2: If(X) begin NextState=0; Z=1; end endcase

d. Z = 0; case(state) 0: If(!X) NextState=1; 1: If(X) NextState=0 else NextState=2; 2: If(X) begin NextState=0; Z=1; end endcase

e. case(state) 0: If(!X) NextState=1; 1: If(X) NextState=0 else NextState=2; 2: If(X) begin NextState=0; Z=1; end endcase

"001" detector Z CLK "001" detector Z CLK