Question: We wish to implement a circuit that has input w and output z. The circuit must generate z = 1 when the previous four values

We wish to implement a circuit that has input w and output z. The circuit must generate z = 1 when the previous four values of w were 1001 or 1111; otherwise z = 0. (a) Give a Moore FSM model for the system. (b) Give a circuit implementation of this using D flip-flops and necessary logic gates. (c) Give an implementation of this system in Verilog

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