We would like to improve the estimated average memory latency in Example 10.1. Sup- pose, instead of SDRAMs, the memory unit is designed using DDR SDRAMs. Recalcu- late the average memory latency.

example-10.1 Given the following infor- mation, estimate its average memory latency. Also assume peak main memory bandwidth.

Ic and Dc: Latency = 1 ns, hit ratio = 0.95 (assume the same for both caches) L2 cache: Cache line = 32 B, latency = 3 ns, hit ratio = 0.9 Main memory: 400 MHz SDRAM, 32-bit (4B) data bus