what does it mean for a signal to be declared 'tri' in SystemVerilog?

adder module for the the serial two's complementer from use Write write an HDL module for the circuit in Exercise 3.31. write an HDL module for the circuit in Exercise 3.32. Write an HDL module for the circuit in Exercise 3.33 Write an HDL module for the circuit in Exercise 3.34. You may from Section 4.2.5 Exercises wing exercises are specific to Systemverilog. .46 what does it mean for a signal to be declared tri in SystemVerilog? .47 Rewrite the syncbad module from HDL Example 4.29. Use ing assignments, but change the code to produce a correct synchronizer flip-flops. Consider the following two SystemVerilog modules. Do they have function? Sketch the hardware each one implies. le codel (input logic clk, a, b, c. output logic y); ic x ays-ff (posedge clk) begin a & b