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one digit 7 segment diplay

- 3 X BOX 7 ISE Project Navigator (M.70d) - C-WXilinx 1211121.xise - [121.7"] File Edit View Project Source Process Tools Window Layout Help x POE Design 1 timescale ins/ips View: Implementas Semula 2 3 A Hierarchy module 121(W, X, Y, Z, ANO, ANI, ANZ, AN3, A,B,C,D,E,F,G): 4 121 input W, X, Y, 2; 5 xc3s500e-4f9320 output reg ANO: 6 121 (121) output reg AN: output reg AN2: 121.ucf @ output reg AN3; 9 output A, B, C, D,E,,G: A 10 > 11 12 assign A- (WS-X6- Y2) (W& XS-Y-2): 13 assign B - (-W 6X6- Y2) 1 - 6 X & Y 6-2): 14 assign C = ( WXGY & -Z): 15 assign D - (X6Y & 2) I (W & XY 6-2) (WSX&Y & 2): 16 assign E- (-W & 2) (W EX-Y) (X -Y & 2); 17 assign --W-X & 2) (W X Y) (WAY & 2): 18 assign G = (- 6 X 6 -Y) (W6X6 Y6 2): Run Faled: Synthesis 19 20 Processes: 121 21 Design Summary/Reports 22 always (*) Design Utilities 23 begin User Constraints 24 ANO0; Synthesize - XST 25 ANI-1: Implement Design 26 AN21; Generate Programming File 27 AN31; Configure Target Device 20 end CH Analyze Design Using Chip 29 30 endmodule 31 321 AWWW A 000 Start Design Fles ISE Design Sute InfoCenter Design Summary (Synthesized) 121. 121.cf 121.5 Errors ERROR: HD.Compilezo:168 - 12.7" line 22 No signals referenced in statement with implicat sensitivity list Console Erors Warnings Find in Fles Results In 32 Col 1 Verilog