What is wrong with the following code for a half adder that must add

if add signal equals $1?($choose the correct answer and why$)$beginbegin carry $=$ x & y;else sum $=0$;end

enda$)$ It will compile but will not simulate correctly

b$)$ It will compile and simulate correctly but will not synthesize correctly

c$)$ It will work correctly in simulation and in synthesis

d$)$ It will not even compile