When clock and data are from SoC to SPI, what is the setup time$($in ps$)$ seen at SPI device interface ports $($marked$)$ with an arrow.

Clock from debugger launches data to debugger to be captured internally on same clock. There is a variable delay element $($Tv$)$ on capture branch. What is the max delay after which the hold is seen

Assume buffer delay of $0\mathrm{.}05$ns$($min$)$ and $0\mathrm{.}1$ ns $($max$),$ net delays of $0.$ Flop setup time : $0\mathrm{.}1$ ns $,$ Flop Hold time ; $0\mathrm{.}05$ ns and flop CP rarrQ:$0\mathrm{.}05$ns$.$

Pick ONE option

a$.$ tv$>0\mathrm{.}3$ns b$.$tv$>0\mathrm{.}4$ns c$.$tv$<mn>0</mn><mn>.</mn><mn>3</mn>$ns d$.$tv$<mn>0</mn><mn>.</mn><mn>4</mn>$ns