SoC

SPI slave device

$\backslash$begin$\{$tabular$\}\{$ll$\}$

$\backslash$hline$\backslash ($ D $\backslash )$ & $\backslash ($ Q $\backslash )\backslash \backslash$

$\backslash ($ C l k $\backslash )$ & $\backslash ($ Q $\backslash )\backslash \backslash$

$\backslash$end$\{$tabular$\}$

When clock and data are from SoC to SPI, is the setup time$($in ps$)$ seen at SPI device interface ports $($marked$)$ with