When creating behavioural descriptions in Verilog, you generally need to estimate worst-case propagation delays of what you expect the resulting circuit would have. In this question, you'll do it for a circuit that adds 1 to a 3-bit number. Plan a circuit to add 1 to a 3-bit number. The circuit will have as input 3 wires (in[2], in[1], in[0]) that are a 3-bit number. It will have as output 3 wires (out[2], out[1], out[0]) that are a 3-bit number that is equal to the input plus 1. You do not need to submit a diagram of the circuit. Instead, provide the answer as in the following table. Provide the equation and propagation delay for each of the 3 outputs, as well as the maximum of those 3 propagation delays. Equation Propagation Delay Output out[2] out11 out[0] Maximum Propagation Delay: When creating behavioural descriptions in Verilog, you generally need to estimate worst-case propagation delays of what you expect the resulting circuit would have. In this question, you'll do it for a circuit that adds 1 to a 3-bit number. Plan a circuit to add 1 to a 3-bit number. The circuit will have as input 3 wires (in[2], in[1], in[0]) that are a 3-bit number. It will have as output 3 wires (out[2], out[1], out[0]) that are a 3-bit number that is equal to the input plus 1. You do not need to submit a diagram of the circuit. Instead, provide the answer as in the following table. Provide the equation and propagation delay for each of the 3 outputs, as well as the maximum of those 3 propagation delays. Equation Propagation Delay Output out[2] out11 out[0] Maximum Propagation Delay