Question: // when i pressed the key this code below displayed 4 digital numbers (1111, 2222, 3333, .. 9999). How can I fix this code to
// when i pressed the key this code below displayed 4 digital numbers (1111, 2222, 3333, .. 9999). How can I fix this code to count from 1 to 9 with single number ?
// This code is performed for microcontroller SAMD20J18
#include
// Void functions
void wait(int t);
void Simple_Clk_Init(void);
// Global Variables
volatile int count = 0; // important to keep volatile int main (void)
{
// Set micro-controller clock to 8Mhz
Simple_Clk_Init();
// Set the base address for the Port structure to PORT_INSTS or 0x41004400
Port *ports = PORT_INSTS;
// Set the group's offset for the structure PortGroup in this case it is for group[0] or groupA
// Group A offset of 0x00 // Group B offset of 0x80
PortGroup *portAs = &(ports->Group[0]); PortGroup *portBs = &(ports->Group[1]);
portAs ->DIRSET.reg = PORT_PA07 | PORT_PA06 | PORT_PA05| PORT_PA04; portAs ->DIRCLR.reg = PORT_PA19 | PORT_PA18 | PORT_PA17| PORT_PA16;
portBs->DIRSET.reg = PORT_PB00|PORT_PB05|PORT_PB04|PORT_PB03|PORT_PB06|PORT_PB07|PORT_PB01|PORT_PB02; portBs->OUTSET.reg = PORT_PB00|PORT_PB05|PORT_PB04|PORT_PB03|PORT_PB06|PORT_PB07;
portAs->PINCFG[19].reg = PORT_PINCFG_INEN | PORT_PINCFG_PULLEN; portAs->PINCFG[18].reg = PORT_PINCFG_INEN | PORT_PINCFG_PULLEN; portAs->PINCFG[17].reg = PORT_PINCFG_INEN | PORT_PINCFG_PULLEN; portAs->PINCFG[16].reg = PORT_PINCFG_INEN | PORT_PINCFG_PULLEN;
while(1)
{
portAs->OUTCLR.reg = PORT_PA07; //sets pa07 high portAs->OUTSET.reg = PORT_PA05|PORT_PA06|PORT_PA04;
if(portAs->IN.reg & PORT_PA19 ) //displays1
{ portBs->OUTSET.reg = PORT_PB00|PORT_PB05|PORT_PB04|PORT_PB03|PORT_PB06|PORT_PB07; portBs->OUTCLR.reg=PORT_PB02|PORT_PB01;
}
if (portAs->IN.reg&PORT_PA18) //displays 2
{ portBs->OUTSET.reg = PORT_PB07|PORT_PB05|PORT_PB02; portBs->OUTCLR.reg=PORT_PB00|PORT_PB01|PORT_PB06|PORT_PB04|PORT_PB03; } if (portAs->IN.reg & PORT_PA17) // displays 3 { portBs->OUTSET.reg = PORT_PB05|PORT_PB04|PORT_PB07; portBs->OUTCLR.reg=PORT_PB00|PORT_PB01|PORT_PB06|PORT_PB03|PORT_PB02; } if (portAs->IN.reg & PORT_PA16) //displays A
{ portBs->OUTSET.reg = PORT_PB03|PORT_PB07; portBs->OUTCLR.reg=PORT_PB00|PORT_PB05|PORT_PB01|PORT_PB06|PORT_PB04|PORT_PB02; } portAs->OUTCLR.reg = PORT_PA06; // sets pa06 high portAs->OUTSET.reg = PORT_PA04|PORT_PA05|PORT_PA07;
//series of if statements to check inputs
if(portAs->IN.reg & PORT_PA19 ) //displays 4
{ portBs->OUTSET.reg = PORT_PB07|PORT_PB00|PORT_PB04|PORT_PB03; portBs->OUTCLR.reg=PORT_PB05|PORT_PB06|PORT_PB01|PORT_PB02; } if (portAs->IN.reg&PORT_PA18) //displays 5
{
portBs->OUTSET.reg = PORT_PB07|PORT_PB01|PORT_PB04; portBs->OUTCLR.reg=PORT_PB00|PORT_PB05|PORT_PB06|PORT_PB02|PORT_PB03;
}
if (portAs->IN.reg & PORT_PA17) //displays 6
{
portBs->OUTSET.reg = PORT_PB07|PORT_PB00|PORT_PB01; portBs->OUTCLR.reg=PORT_PB05|PORT_PB04|PORT_PB03|PORT_PB02|PORT_PB06;
}
if (portAs->IN.reg & PORT_PA16) // displays 6
{
portBs->OUTSET.reg = PORT_PB07|PORT_PB00|PORT_PB01; portBs->OUTCLR.reg=PORT_PB05|PORT_PB04|PORT_PB03|PORT_PB02|PORT_PB06;
}
portAs->OUTCLR.reg = PORT_PA05; // sets pa05 high portAs->OUTSET.reg = PORT_PA04|PORT_PA06|PORT_PA07;
//series of if statements to check inputs
if(portAs->IN.reg & PORT_PA19 ) // displays 7
{
portBs->OUTSET.reg = PORT_PB07|PORT_PB06|PORT_PB05|PORT_PB04|PORT_PB03; portBs->OUTCLR.reg=PORT_PB00|PORT_PB01|PORT_PB02; }
if (portAs->IN.reg&PORT_PA18) // displays 8
{
portBs->OUTSET.reg = PORT_PB07; portBs->OUTCLR.reg=PORT_PB00|PORT_PB02|PORT_PB06|PORT_PB05|PORT_PB04|PORT_PB03|PORT_PB01;
}
if (portAs->IN.reg & PORT_PA17) //displays 9
{
portBs->OUTSET.reg = PORT_PB07|PORT_PB04|PORT_PB03; portBs->OUTCLR.reg=PORT_PB00|PORT_PB02|PORT_PB06|PORT_PB05|PORT_PB01;
}
if (portAs->IN.reg & PORT_PA16)// displays p
{
portBs->OUTSET.reg = PORT_PB07|PORT_PB04|PORT_PB03; portBs->OUTCLR.reg=PORT_PB00|PORT_PB02|PORT_PB06|PORT_PB05|PORT_PB01;
}
portAs->OUTCLR.reg = PORT_PA04; // sets pa04 high portAs->OUTSET.reg = PORT_PA05|PORT_PA06|PORT_PA07;
//if statements to check inputs
if(portAs->IN.reg & PORT_PA19 )
{ portBs->OUTSET.reg = PORT_PB07|PORT_PB04|PORT_PB03; portBs->OUTCLR.reg=PORT_PB00|PORT_PB02|PORT_PB06|PORT_PB05|PORT_PB01; } if (portAs->IN.reg&PORT_PA18)
{ portBs->OUTSET.reg = PORT_PB07|PORT_PB04|PORT_PB03; portBs->OUTCLR.reg=PORT_PB00|PORT_PB02|PORT_PB06|PORT_PB05|PORT_PB01; } if (portAs->IN.reg & PORT_PA17)
{ portBs->OUTSET.reg = PORT_PB07|PORT_PB04|PORT_PB03; portBs->OUTCLR.reg=PORT_PB00|PORT_PB02|PORT_PB06|PORT_PB05|PORT_PB01;
} if (portAs->IN.reg & PORT_PA16)
{ portBs->OUTSET.reg = PORT_PB07|PORT_PB04|PORT_PB03; portBs->OUTCLR.reg=PORT_PB00|PORT_PB02|PORT_PB06|PORT_PB05|PORT_PB01;
}
}
}
// Time delay function
void wait(int t)
{
count = 0; while (count < t*1000)
{ count++; }
}
// Simple Clock Initialization - Do Not Modify - //
void Simple_Clk_Init(void)
{
/* Various bits in the INTFLAG register can be set to one at startup. This will ensure that these bits are cleared */ SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
SYSCTRL_INTFLAG_DFLLRDY; system_flash_set_waitstates(0); // Clock_flash wait state = 0 SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; // for OSC8M initialization temp.bit.PRESC = 0; // no divide, i.e., set clock=8Mhz (see page 170) temp.bit.ONDEMAND = 1; // On-demand is true temp.bit.RUNSTDBY = 0; // Standby is false SYSCTRL->OSC8M = temp; SYSCTRL->OSC8M.reg |= 0x1u << 1; // SYSCTRL_OSC8M_ENABLE bit = bit-1 (page 170) PM->CPUSEL.reg = (uint32_t)0; // CPU and BUS clocks Divide by 1 (see page 110) PM->APBASEL.reg = (uint32_t)0; // APBA clock 0= Divide by 1 (see page 110) PM->APBBSEL.reg = (uint32_t)0; // APBB clock 0= Divide by 1 (see page 110) PM->APBCSEL.reg = (uint32_t)0; // APBB clock 0= Divide by 1 (see page 110)
PM->APBAMASK.reg |= 01u<<3; // Enable Generic clock controller clock (page 127)
/* Software reset Generic clock to ensure it is re-initialized correctly */ GCLK->CTRL.reg = 0x1u << 0; // Reset gen. clock (see page 94) while (GCLK->CTRL.reg & 0x1u ) { /* Wait for reset to complete */ }
// Initialization and enable generic clock #0 *((uint8_t*)&GCLK->GENDIV.reg) = 0; // Select GCLK0 (page 104, Table 14-10) GCLK->GENDIV.reg = 0x0100; // Divide by 1 for GCLK #0 (page 104) GCLK->GENCTRL.reg = 0x030600; // GCLK#0 enable, Source=6(OSC8M), IDC=1 (page 101) }
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