When studying latch circuits, you will come across many references to$$set$$and$$reset$$logic states. The proper way to describe it is$...$

Group of answer choices

A latch is considered set when its output $($Q$)$ is high, and reset when its output $($Q$)$ is low.

A latch is considered set when its output $($Q$)$ is low, and reset when its output $($Q$)$ is high

A latch is considered set when its output $($Q$)$ toggles from high to low

A latch is considered reset when its output $($Q$)$ toggles from low to high