Which component does following verilog module implements?

A$.$ Decoder

B$.$ Multiplexer

C$.$ Shift Register

D$.$ Multiplier

E$.$ Priority Encoder

timescale $1n\frac{s}{1}ns$

emodule component

$($

input wire $1$:$0$ a$.$

input wire $b,$

output reg $[3$:$0]C$

I:

always $($a$)*$

if $)==(1,b0$

$c=4*b0000$;

else if $)==(2^{\text{'}}b00$

$c=4^{\text{'}}b0001$;

else if $)==(2*b01$

$c=4^{\text{'}}b0010$;

else if $)==(2,b10$

$c=4*b0100$;

else

$c=4*b1000$;

endmodule