Question: Why are page tables problematic for high bit - width CPUs ( e . g . 6 4 - bit CPUs ) ? Group of

Why are page tables problematic for high bit-width CPUs (e.g.64-bit CPUs)?
Group of answer choices
They reintroduce external fragmentation.
The TLB will present a bottleneck for page lookups.
The required page table size will likely exceed the amount of physical memory available.
The MMU becomes a bottleneck during page lookups.
Page tables become vulnerable to chatGPT attacks.\

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