Question: Why can the instruction memory and the data memory share the same address bus in Cortex - M 3 , Cortex - M 4 and

Why can the instruction memory and the data memory share the same address bus in Cortex-M3, Cortex-M4 and Cortex-M7? In other words, why can we put the instruction memory and the data memory in the same memory address space (i.e. Unified address space within Harvard architecture)?
Why can the instruction memory and the data memory share the

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