Why using cache memory? What is the typical size of a cache memory page? Order from slowest to fastest: L1, L2, L3 cache. Order from smallest to biggest: L1, L2, L3 cache. Does the core stall if producing a read-miss? Does the core stall if producing a write-miss? Why is a write buffer necessary? Given a RAM with 64 (cache page size) bytes *32 memory pages and a cache with 8 memory pages. Explain the addressing with direct mapped cache. What are tags (direct mapped cache) and why do we need them