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2. The VHDL code given below is describing a block diagram of a circuit. Draw the architecture RTL that is described by this code. (15 Marks) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY variable_rotator is \( \begin{array}{l} \text { PORT( } \\ \text { A : IN STD_LOGIC_VECTOR(15 downto } 0) ; \\ \text { B : IN STD_LOGIC_VECTOR }(3 \text { downto } 0) ; \\ \text { C : OUT STD_LOGIC_VECTOR(15 downto } 0) \\ ) ;\end{array} \) END variable rotator: ARCHITECTURE structural OF variable_rotator IS TYPE array16 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL Al : array 16; SIGNAL Ar : array16; BEGIN Al(0)