Work your assigned combinational logic design problem using the DirectVHDL simulator and the following procedure:

Work out the logic design for your assigned problem, including a block diagram for the main module showing inputs, outputs, and internal connections.

Write VHDL code that describes your design.

Simulate and debug the VHDL code.

Print out a simulator listing that verifies the correct operation of your design for the prescribed test sequences.

A half adder is a circuit that can add two bits at a time to produce a sum and a carry. Design a half adder using only two gates. Write an entity$-$architecture pair to implement the half adder. Now write an entity$-$architecture pair to implement a full adder using two instances of your half adder and an OR gate. Use the port definitions specified below:

For the half adder: port $($a$,$ b: in bit; s$,$ c: out bit$)$;

For the full adder: port $($a$,$ b$,$ cin: in bit; sum, cout: out bit$)$;

Simulate your code and test it using the following inputs: a b cin $=001,011,111,110,100$