Write a simulation functions for AND gate and OR gate, e$.$g$.,$

int AND$\_$gate $($int a$,$ int b$)\{....\}$

int OR$\_$gate $($int a$,$ int b$)\{....\}$

$2.$ Write a simulation function for the full$\_$adder. e$.$g$.,$

int full$\_$adder $($int a$,$ int b$,$ int cin, int &cout$)\{....\}$

$3.$ Write a simulation function for the $2$x$1$ mux, e$.$g$.,$

int mux$\_2$x$1($int x$1,$ int x$2,$ int sel$)\{....\}$

$4.$ Write a simulation function for the $4$x$1$ mux, e$.$g$.,$

int mux$\_4$x$1($int x$1,$ int x$2,$ int x$3,$ int x$4,$ string sel$)\{....\}$

$5.$ Write a simulation function for the $1$bit$\_$ALU, e$.$g$.,$

int ALU$\_1$bit $($int a$,$ int b$,$ int B$\_$inv, int cin, string op$,$ int &cout$)\{....\}$

$6.$ Write a driver module $($main function$)$ and test your $1-$bit ALU for correctness with all

possible input value combinations $($total $32$ cases to test$).$

The driver should display input values and the corresponding output values for each

test case, i$.$e$.,$

a b cin Binv op result cout

$-------------------------------------------------------------------$

$00000000$

$00100000$

$.....................................8$ cases for AND

$11100011$

$000001.......$

$001001.......$

$.....................................8$ cases for OR

$111001.......$

$000010.......$

$001010.......$

$.....................................8$ cases for Add

$111010.......$

$000110.......$

$001110.......$

$.....................................8$ cases for Sub

$111110.......$