Question: Write a System Verilog model of a 4-to-2 bit priority encoder, using continuous assign statements. Write a SystemVerilog testbench model that tests your priority encoder

Write a System Verilog model of a 4-to-2 bit priority encoder,

Write a System Verilog model of a 4-to-2 bit priority encoder, using continuous assign statements. Write a SystemVerilog testbench model that tests your priority encoder module by applying all possible input combinations

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