Question: Write a Verilog code and use Tang Nano 9 k FPGA that will generate PWM signal at frequency 1 ABC Hz where ABC is the

Write a Verilog code and use Tang Nano 9k FPGA that will generate PWM signal at frequency 1 ABC Hz where
ABC is the last three digits of your student ID. Duty cycle is 50% Measure the generated signal using Saleae
logic analyzer and copy past the picture showing the frequency and duty cycles
Save AS the file in PDF and
/Paste the pictures of the setup showing Tang Nano 9K FPGA and Logic Analyzer connected
//****** Copy Paste the picture of Logic Analyzer screen showing frequency and 50% duty cycle ^(******//)
//****** Copy Paste the FloorPlanner IO Constraints Table ^(******//)

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