Write a Verilog module that accepts an eight-byte sequence on eight-bit input in, where the first byte is signaled by a single-bit start signal. Your module should assert a single-bit done signal on the cycle after the last byte is input. In the same cycle, it should assert a single-bit in sequence signal if the eight bytes were in descending sequence; that is, if the i + 1st byte is one less than the i th byte, b_i+1 = b_i-1 for i, from 1 to 7