Question: Write a Verilog module that implements the following Boolean equation: f1 = a * b * c' + a * c + b * c

Write a Verilog module that implements the following Boolean equation:

f1 = a * b * c' + a * c + b * c

Simplify the above expression; write another module to implement it as f2. Write a test bench to check whether f1 and f2 are identical with different values of a, b and c.

Write the programs first using iverilog, then repeat it using Xilinx ise

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