Question: Write a VHDL code for the implementation of a dual-port 1K x 8 RAM memory, the block diagram of which allows multiple reads or writes

Write a VHDL code for the implementation of a dual-port 1K x 8 RAM memory, the block diagram of which allows multiple reads or writes at the same time.
(Enabled; E: global enable input, WE: write enable input, Address_A: Write address / primary read address input, Address_B: Dual read address input, O_A: Primary output port, O_B: Dual output port.)

Adres_A Adres_B O_A E RAM WE O_B Data_Giris CLK

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