Below are VHDL programs that implement a D flip-flop and a JK flip-flop. Accordingly, write a VHDL program that realizes the circuit given in the figure below.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_FF is port (D, clk: in std logic; 0, Qd: out std_logic); end D_FF; D. architecture Behavioral of D_FF CLK is begin process (clk, D) begin if (clk='1' and clk'event) then Q