Below are VHDL programs that implement a D flip-flop and a JK flip-flop. Accordingly, write a VHDL program that realizes the circuit given in the figure below.

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_FF is port (D, clk: in std logic; 0, Qd: out std_logic); end D_FF; D. architecture Behavioral of D_FF CLK is begin process (clk, D) begin if (clk='1' and clk'event) then Q<=D; Qd<=not D; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity JK FF is PORT ( J, K, clk: in std logic; Q, Qd: out std_logic); end JK FF; architecture Behavioral of JK_FF is signal durum:std_logic; begin process (J, K, clk) begin if (clk='1' and clk'event) then if (J='0' and K='0') then durum<=durum; elsif(J='1' and K='1') then durum<= not durum; elsif(J='0' and K='1') then durum<='0'; else durum<='1'; end if; end if; Q<= durum; Qd <=not durum; end process; end Behavioral; 10 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity D_FF is port (D, clk: in std logic; 0, Qd: out std_logic); end D_FF; D. architecture Behavioral of D_FF CLK is begin process (clk, D) begin if (clk='1' and clk'event) then Q<=D; Qd<=not D; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity JK FF is PORT ( J, K, clk: in std logic; Q, Qd: out std_logic); end JK FF; architecture Behavioral of JK_FF is signal durum:std_logic; begin process (J, K, clk) begin if (clk='1' and clk'event) then if (J='0' and K='0') then durum<=durum; elsif(J='1' and K='1') then durum<= not durum; elsif(J='0' and K='1') then durum<='0'; else durum<='1'; end if; end if; Q<= durum; Qd <=not durum; end process; end Behavioral; 10