Write a VHDL program to implement a 512 8-bit RAM block (with main code and constrains file)

(You can refer to VHDL code for ROM here)

entity romtest is

Port ( addr1: in std_logic_vector (3 downto 0); addr2: in std_logic_vector (3 downto 0);

result: out unsigned (8 downto 0)

);

end romtest;

architecture Behavioral of romtest is

signal data1, data2: std_logic_vector (7 downto 0);

signal dataext: unsigned (8 downto 0);

component rom1

port ( address : in std_logic_vector(3 downto 0);

data : out std_logic_vector(7 downto 0) );

end component;

begin

U1: rom1 port map(addr1, data1);

U2: rom1 port map(addr2, data2);

dataext <= '0' & unsigned(data1);

result <= '0' & unsigned(data2)+dataext;

end Behavioral;

ROM program:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity rom1 is

port ( address : in std_logic_vector(3 downto 0);

data : out std_logic_vector(7 downto 0) );

end rom1;

architecture Behavioral of rom1 is

type mem is array ( 0 to 2**4 - 1) of std_logic_vector(7 downto 0);

constant my_Rom : mem := (

0 => "00000000", 1 => "00000001", 2 => "00000010", 3 => "00000011",

4 => "00000100", 5 => "11110000", 6 => "11110000", 7 => "11110000",

8 => "11110000", 9 => "11110000", 10 => "11110000", 11 => "11110000",

12 => "11110000", 13 => "11110000", 14 => "11110000", 15 => "11110000");

begin

process (address)

begin

case address is

when "0000" => data <= my_rom(0); when "0001" => data <= my_rom(1);

when "0010" => data <= my_rom(2); when "0011" => data <= my_rom(3);

when "0100" => data <= my_rom(4); when "0101" => data <= my_rom(5);

when "0110" => data <= my_rom(6); when "0111" => data <= my_rom(7);

when "1000" => data <= my_rom(8); when "1001" => data <= my_rom(9);

when "1010" => data <= my_rom(10); when "1011" => data <= my_rom(11);

when "1100" => data <= my_rom(12); when "1101" => data <= my_rom(13);

when "1110" => data <= my_rom(14); when "1111" => data <= my_rom(15);

when others => data <= "00000000";

end case;

end process;

end Behavioral;