Question: Write an HDL module below that implements this FSM. module fsm( input logic clk, input logic reset, input logic up, output logic [2:0] grayCode );

Write an HDL module below that implements this FSM. module fsm( input logic clk, input logic reset, input logic up, output logic [2:0] grayCode );

State Table of FSM:

Number

Gray Code

0

0

0

0

1

0

0

1

2

0

1

1

3

0

1

0

4

1

1

0

5

1

1

1

6

1

0

1

7

1

0

0

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