Question: Write the constraint file PreLab 6 module Question 2. (X.9.9.) Input [10] x.y. output reg [30]. 4, output req [6.olci always @ x) begin Case

Write the constraint file
Write the constraint file PreLab 6 module Question 2. (X.9.9.) Input [10]
x.y. output reg [30]. 4, output req [6.olci always @ x) begin

PreLab 6 module Question 2. (X.9.9.) Input [10] x.y. output reg [30]. 4, output req [6.olci always @ x) begin Case (x) 2'600:0=4600011 liturn on display o 2'601.9-4.5000 ill turn on display 1 2' b10:9=4'60100; liturn on display 2 2'611:9=4 b1000, ll turn on display 3 default: a = 4'50000; endcase end alwaysa (y) begin casety) 24600:6-760001110: || Display letter "L" 2'602:(-1'61011011, Il display better *$* 2'610C-1'60000000 | TUIN GIT LEDs 2'611:61160111110; llpisplay letter default :c1'60000000; endcase end endmodule Constraints File: The constraints file maps the inputs and outputs of your design with input switches and, in this experiment, 7-segment (output) displays. You are required to map the input bits X[1], X[0], Y[1], Y[0] (in that order from left to right) to the rightmost 4 logic switches on the Basys3 board. 1 6 Now refer to the Figure 16 of the Basys3 Manual. You will see that pins AN3, ..., ANO are labeled W4, , U2 and pins CA, , CG, DP are labeled W7, ..., U7, 17. Write constraint files for your module outputs accoringly. PreLab 6 module Question 2. (X.9.9.) Input [10] x.y. output reg [30]. 4, output req [6.olci always @ x) begin Case (x) 2'600:0=4600011 liturn on display o 2'601.9-4.5000 ill turn on display 1 2' b10:9=4'60100; liturn on display 2 2'611:9=4 b1000, ll turn on display 3 default: a = 4'50000; endcase end alwaysa (y) begin casety) 24600:6-760001110: || Display letter "L" 2'602:(-1'61011011, Il display better *$* 2'610C-1'60000000 | TUIN GIT LEDs 2'611:61160111110; llpisplay letter default :c1'60000000; endcase end endmodule Constraints File: The constraints file maps the inputs and outputs of your design with input switches and, in this experiment, 7-segment (output) displays. You are required to map the input bits X[1], X[0], Y[1], Y[0] (in that order from left to right) to the rightmost 4 logic switches on the Basys3 board. 1 6 Now refer to the Figure 16 of the Basys3 Manual. You will see that pins AN3, ..., ANO are labeled W4, , U2 and pins CA, , CG, DP are labeled W7, ..., U7, 17. Write constraint files for your module outputs accoringly

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