Verilog problem

Design a timer counter that provides a running display in milliseconds. On startup or downloading of the .sof file the timer should display 0 and increment every millisecond until it reaches 6789 milliseconds (6.789 sec). The next output should then be 0000 and the whole process repeats. Your task is to instantiate the Timer and DisplayTimerError modules and add some logic of your own in YourPart module.

module YourPart(iClk, iRst, iErrorCodes, iEnableDisplay, iFreezeDisplay, oHEX0, oHEX1, oHEX2, oHEX3);

input iClk, iRst, iEnableDisplay, iFreezeDisplay;

input [1:0] iErrorCodes;

output [6:0] oHEX0, oHEX1, oHEX2, oHEX3;

// Your code goes here

endmodule

//**********************************************************************************************************

// MODULE: DisplayTimerError

// DESCRIPTION: Displays the perception time in msec if there is no error. Otherwise the error is displayed

// on 4 seven segment displays. Errors are:

// button error (Err1): the wrong button was pressed by the user

// timeout error (Err2): the user took longer than 5 seconds to respond.

//**********************************************************************************************************

module DisplayTimerError(iClk, iButtonError, iEnable, iFreezeTimer, iTimer_msec, oHEX0, oHEX1, oHEX2, oHEX3);

input iClk, iEnable, iFreezeTimer;

input [1:0] iButtonError;

input [15:0] iTimer_msec;

output [6:0] oHEX0, oHEX1, oHEX2, oHEX3;

reg [15:0] display_time;

always@(posedge iClk)

if (iFreezeTimer)

display_time <= iTimer_msec;

Display4BCD_Error d0(display_time, iEnable, iButtonError, oHEX0, oHEX1, oHEX2, oHEX3);

endmodule

// MODULE: Timer

// DESCRIPTION: For a 50 MHz iClk, oTime_msec16 is the 16 bit elapsed

// time in milliseconds since the last time iRst=1.

//**********************************************************************************************************

module Timer(iClk, iRst, oTime_msec16);

input iClk, iRst;

output reg [15:0] oTime_msec16;

reg [15:0] CE_cntr;

wire CE_msec = (CE_cntr == 50000 - 1); // 1 for one clock cycle every 50,000 clock cycles

always @(posedge iClk) // Generate clock enable CE_msec

if (iRst || CE_msec) CE_cntr <= 0;

else CE_cntr <= CE_cntr + 1'b1;

always @(posedge iClk) // increment time in msec.

begin

if (iRst) oTime_msec16 <= 0;

else if (CE_msec)

oTime_msec16 <= oTime_msec16 + 1'b1; // increment every msec

end

endmodule

// MODULE: Display4BCD_Error

// DESCRIPTION: Displays 14 bit value as 4 decimal digits each a 7 segment display.

// When iError is non zero, the error number is displayed instead.

// When iEn=0 displays are blanked.

//**********************************************************************************************************

module Display4BCD_Error(iValue14bit, iEn, iError, oHEX0, oHEX1, oHEX2, oHEX3);

input [13:0] iValue14bit; // binary value to display

input iEn; // displays when 1, blank when 0

input [1:0] iError; // two bit error code for display, 00 no error.

output [6:0] oHEX0, oHEX1, oHEX2, oHEX3;

// Decimal digits on 7 segment displays, oHEX3 is most significant

// if Value_in >= 9999, display shows 9999

wire [6:0] HEX0t, HEX1t, HEX2t, HEX3t, HEX0e;

wire [19:0] BCD20;

wire [15:0] BCD16;

Bin2BCD b0(iValue14bit, BCD20);

Hexdisplay H0(BCD20[3:0], HEX0t);

Hexdisplay H1(BCD20[7:4], HEX1t);

Hexdisplay H2(BCD20[11:8], HEX2t);

Hexdisplay H3(BCD20[15:12],HEX3t);

wire error_enable = !(iError == 2'b00);

parameter [6:0] E7 = 7'b0000110;

parameter [6:0] r7 = 7'b0101111;

Hexdisplay H5(iError, HEX0e);

assign oHEX0 = (iEn ? (error_enable? HEX0e: HEX0t) : 7'b1111111);

assign oHEX1 = (iEn ? (error_enable? r7: HEX1t) : 7'b1111111);

assign oHEX2 = (iEn ? (error_enable? r7: HEX2t) : 7'b1111111);

assign oHEX3 = (iEn ? (error_enable? E7: HEX3t) : 7'b1111111);

endmodule

//**********************************************************************************************************

// MODULE: Bin2BCD

// DESCRIPTION: Converts a 14 bit binary number into decimal with 5 BCD digits.

// This module minimises resource usage by using shifts, comparisons and adds without / % operators.

// It has many levels of logic, so is slow yet much quicker than can be seen by the human eye!

// the loops are unrolled before synthesis and new signal name versoins are used for LHS of

// assignments on each iteration. The last versions are then used to update oBCD20.

// After synthesis look at Bin2BCD using Quartus: Tools->Netlist viewers->RTL viewer.

//**********************************************************************************************************

module Bin2BCD(iBin14, oBCD20);

input [13:0] iBin14;

output reg [19:0] oBCD20;

reg [13:0] bin14;

integer i, j;

reg [3:0] temp;

always@(iBin14) begin

oBCD20 = 20'b0;

bin14 = iBin14;

for(i=0; i<14; i=i+1) begin // When synthesised the "for" statement is unwrapped to 14 levels of logic.

// Add 3 to BCD digits >= 5. After considering the upcoming *2 due to the shift left below,

// this converts the hexadecimal weighting of 16 between digits to decimal with a weighting of 10 between digits.

for (j=0; j<5; j=j+1) begin // Each BCD digit updated independently: ie parallel logic.

temp = {oBCD20[4*j+3], oBCD20[4*j+2], oBCD20[4*j+1], oBCD20[4*j] }; //temp is 4 bit BCD digit

if (temp > 4)

{oBCD20[4*j+3], oBCD20[4*j+2], oBCD20[4*j+1], oBCD20[4*j] } = temp + 4'd3;

end

// shift left one bit

{oBCD20, bin14} = {oBCD20, bin14} << 1;

end

end

endmodule

// MODULE: Hexdisplay

// DESCRIPTION: converts a 4 bit BCD number to 7 segment display format

//**********************************************************************************************************

module Hexdisplay(iBinary4bit, oHex);

input [3:0] iBinary4bit; //the 4 bit BCD number

output reg [6:0] oHex; //7 segment display output

always @(iBinary4bit)

case (iBinary4bit)

0: oHex <= 7'b 1000000;

1: oHex <= 7'b 1111001;

2: oHex <= 7'b 0100100;

3: oHex <= 7'b 0110000;

4: oHex <= 7'b 0011001;

5: oHex <= 7'b 0010010;

6: oHex <= 7'b 0000010;

7: oHex <= 7'b 1111000;

8: oHex <= 7'b 0000000;

9: oHex <= 7'b 0011000;

default: oHex <= 7'b 1111111;

endcase

endmodule