Write the Verilog for the following module:

It should take as input/output:

clk - Clock(1 bit)

reset - Reset (active high) (1 bit)

in_valid - Whether or not the input is valid (1 bit)

in_ready - Whether not the input can be accepted (1 bit)

in_data - Input data (32 bits)

out_valid - Whether or not the output is valid (1 bit)

out_ready - Whether or not the output can be accepted (1 bit)

out_data - Output data (32 bits)

This module should implement a stack. That is, the last data to be inserted should be the first data to go

out. The size of the stack should be up to 4 32-bit words. Simultanious insertion and deletion should be

allowed, but the input should not directly forward to the output. In other words, a pull from the stack at

the same time as a push will pull the existing top of the stack and not the new top of the stack created by the

push.