write verilog and testbench for this dataparh

$2\mathrm{.}3$

DATAPATH DESIGN

To realize the $4-$bit Smart Climate Control system, the Datapath necessitates specific logical operations, comprising a $2-$to$-4$ Line decoder, four $1-$bit AND gates, five $4-$bit $2-$to$-1$ Multiplexers, five $4-$bit registers, two $4-$bit $4-$to$-1$ Multiplexers, and a $4-$bit ALU, as illustrated in Figure $1.$

Figure $4$: Smart Climate Control Datapath

Each component of the Datapath must undergo individual design and simulation before integration into the overarching structure. Interconnections among these components should be established within the top$-$level design SCCS$\_$DATAPATH, employing a hierarchical design methodology.

This approach should adhere to a parametric model, enabling flexibility in adjusting the controller's bit size. Consequently, a parameterized Verilog code should be written to define the Datapath. The assignment of signals such as CLK and others should align with the directives outlined in section $2\mathrm{.}4.$

The control signals and Datapath operations:

wrt$\_$addr signal provides an address to activate the required register as stated in Table $1.$

Table $1$:$2-$to$-4$ Decoder Operation.

$\backslash$table$[[$wrt addr,Registers$],[$A$,$B$,$REG$\_3,$REG$\_2,$REG$\_1,$REG$\_0,,],[0,0,0,0,0,1,,],[0,1,0,0,1,0,,],[1,0,0,1,0,0,,],[1,1,1,0,0,0,,]]$

wrt$\_$en works together with the wrt$\_$addr to select either a new value or hold the previous value.

Toggle$\_$T$/$H also works with the wit$\_$en and wit$\_$addr to set either the Temperature setting or the Humidity Setting.

load$\_$data signal selects either the new Temperature$/$Humidity User$/$Sensor values from the $4\_$to$\_1$ MUX or the ALU output result for feedback.

Input$\_$sel is used to select the User$\_$Temperature, Sensor$\_$Temperature, User$\_$Humidity, Sensor$\_$Humidity. $($Note: we use a $4-$bit data path so these values should lie between $0-15)$

rd$\_$addr$1$ and rd$\_$addr$2$ signals provide the register addresses that are required to perform the CCU operations between two registers using the ccu$\_$opcode provided. The CCU must be designed with the following operations stated in Table $2.$ You can use the behavioural approach to design the CCU.

Table $2$: ALUOpcodes and Instructions.

$\backslash$table$[[$ccu opcode,Opr $1,$Opr $2,$Op$,$Instruction$],[000,-,-,$noop,$-,-],[001,,-,,R[]=,1],[010,,-,$increment,$R[]=,R[]+1$