write Verilog code 2001 for this

Design a 4-bit combinational unsigned integer multiplier based on the parallel architecture shown on Page 15 of Lecture Slides 6, and write a self-checking Verilog testbench to functionally verify your design. Note: a) You can use two slices of 4-bit carry-look-ahead adders to make an 8-bit adder. b) For functional verification, you can use an "inferred" (by using the Verilog multiplication operator *) 4-bit integer multiplier as the reference model. Design a 4-bit combinational unsigned integer multiplier based on the parallel architecture shown on Page 15 of Lecture Slides 6, and write a self-checking Verilog testbench to functionally verify your design. Note: a) You can use two slices of 4-bit carry-look-ahead adders to make an 8-bit adder. b) For functional verification, you can use an "inferred" (by using the Verilog multiplication operator *) 4-bit integer multiplier as the reference model