write Verilog 2001 code for this

Based on Task 1, design a two-stage pipelined integer multiplier by attaching input/output registers, and inserting stage registers, as shown on Page 16 of Lecture Slides 6. To test your design, you must perform both functional verification (software simulation) and hardware validation (FPGA prototyping using the Basys 3 board). Note: For hardware validation, you should use a manual-driven clock and to do so, a debouncer must be used. Verilog source code for the debouncer can be found in the file "button debouncer.v" on the class Canvas site. Based on Task 1, design a two-stage pipelined integer multiplier by attaching input/output registers, and inserting stage registers, as shown on Page 16 of Lecture Slides 6. To test your design, you must perform both functional verification (software simulation) and hardware validation (FPGA prototyping using the Basys 3 board). Note: For hardware validation, you should use a manual-driven clock and to do so, a debouncer must be used. Verilog source code for the debouncer can be found in the file "button debouncer.v" on the class Canvas site