$.$ Write Verilog code for the bit sorter with two inputs described below. This can be in a plain

text file or handwritten. The sorter $($shown as Mi in the figure below$)$ has two inputs a$,$ b and two

outputs x$,$ y$.$

The following table describes the function of this module.

Condition x y

a $$ b a b

a $>$ b b a

The outputs receive values coming from the inputs depending on the condition $($exactly one of

which must be true$).$ It is easy to verify that if a $=$ b$,$ then x $=$ a and y $=$ b; if a $$ b$,$ then the smaller

value goes to x and the larger value goes to y$.$ Thus, this module is a bit sorter with two inputs.

That is$,$ it takes two one$-$bit numbers a$,$ b and rearranges them in outputs x$,$ y in ascending order.

$2$

$2.$ Write Verilog code for the bit sorter with four inputs described below. Connect six copies of

the module from Part $1$ as shown below to form a $4-$input, $4-$output bitonic sorter.

This network will sort the four input bits A$,$ B$,$ C$,$ D to produce four output bits U$,$ V$,$ W$,$ X$.$ If the

Mi$$s sort their $2-$bit inputs in ascending order, then so will the corresponding bitonic sorter. For

example, an input of ABCD $=0101$ produces an output of UVWX $=0011($all zeroes followed by

all ones$).$