Question: Write Verilog code for the circuit M described below The circuit has four inputs x 1 , x 0 , y 1 , y 0

Write Verilog code for the circuit M described below

The circuit has four inputs x

1,

0,

1,

0

that can be viewed as two vector inputs X

= [

1,

0]

and Y

= [

1,

0],

each with two bits.

Circuit M has

11

output bits grouped into a

4 -

bit vector A

= [

3,

2,

1,

0]

and a

7 -

bit vector C

= [

1,

2,

3,

4,

5,

6,

7] .

These output bits are going to be connected to the Basys

3 7 -

segment display inputs AN

3,

2,

1,

0

and CA

,

,

,

,

,

,

,

respectively

(

in that order

) .

Thus, the circuit that you need to design can be described in terms of what should appear on the Basys

3

board

7 -

segment displays. Circuit M is part of a setup as shown below.

(

Last screenshot

)

The two tables below describe the function of circuit M

(

Last screenshot

)

As example of how M works, suppose X

= 01

and Y

= 10,

then display

3

should show the number

8

and all other displays should be off.

Write Verilog code for the circuit M described

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