You are asked to design and draw the logic circuit of an asynchronous up counter with...

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You are asked to design and draw the logic circuit of an asynchronous up counter with pause and reset features. 4-bit variable "A" is used to control pause and reset features. Counter should be paused when A is "0101" and should be reset when A is "1111", but it should continue to count on other values of A. (A = A3A2A1A0) Count value of counter will be shown with 4-bit output Y. CLK → Y3 Asynchronous Up Counter With Pause and Reset АЗ + Y2 A2 → Y1 A1 Features + YO A0 You can only use T-flip-flops, and, nand, or, nor, xor gates. You can use as many gates and flip-flops as you want. Solutions with least amount of gates and flip-flops used will get full credit. (You can write more than 2 input ports on gates such as and, nand, xor) You are asked to design and draw the logic circuit of an asynchronous up counter with pause and reset features. 4-bit variable "A" is used to control pause and reset features. Counter should be paused when A is "0101" and should be reset when A is "1111", but it should continue to count on other values of A. (A = A3A2A1A0) Count value of counter will be shown with 4-bit output Y. CLK → Y3 Asynchronous Up Counter With Pause and Reset АЗ + Y2 A2 → Y1 A1 Features + YO A0 You can only use T-flip-flops, and, nand, or, nor, xor gates. You can use as many gates and flip-flops as you want. Solutions with least amount of gates and flip-flops used will get full credit. (You can write more than 2 input ports on gates such as and, nand, xor)